Shared-Mask Shuttles
Multiple designs share a single reticle field, splitting mask and wafer costs across participants.
- Up to 16 tiles of 5×5 per field
- Minimum design size 2×2 mm
- Target monthly shuttle cadence
RIFSOL · FRONTEND DIVISION · MPW SERVICE
Frontend Division · MPW Service
Share the wafer. Ship your silicon.
Multi Project Wafer prototyping on the RifSol 350–65 nm platform — shared-mask shuttles, 8–12 week turnaround and a direct path to volume production.
350–65 nm8–12 week turnaroundUp to 16 designs per shuttle200 mm wafers
Overview
Your design on our wafer — cost shared, risk shared
Multi Project Wafer (MPW) is the affordable front door to silicon. Instead of committing to a full mask set, several customer designs share one reticle — up to 16 tiles of 5×5 per field — and the mask and wafer costs are split across participants. For most prototyping programs that cuts the cost of first silicon by 60–80%, turning a tape-out from a corporate decision into an engineering iteration.
The service rides on the RifSol frontend platform: 200 mm wafers across CMOS, BCD, HV CMOS, mixed-signal and power-device processes from 350 nm down to 65 nm, with device windows from 1.8 V logic to 1200 V power. A PDK with standard cells, I/O libraries and memory compilers — plus the RifSol IC Design Center — supports you from netlist to GDSII, and the same fab that runs your shuttle provides packaging, test and qualification under one roof.
MPW is not a dead end. Because shuttle prototypes run on the same process, in the same fab, as dedicated production, a proven design scales to full-wafer volume without re-qualification. Shuttles target a monthly cadence based on demand aggregation, and low-volume deliveries of 10–50 packaged units per design make the service practical for startups, universities and fabless teams validating first silicon.
8–12 wk
Tape-out to packaged delivery
16
Designs per shuttle field
350–65 nm
Node window
60–80%
Prototyping cost shared away
Capabilities
What MPW Services delivers
Rapid Turnaround
From GDSII tape-out to validated packaged devices in 8–12 weeks.
- Design review and DRC at intake
- 100% test coverage at delivery
- QFN and BGA packaging options
Process Portfolio
Five process families on one 200 mm platform, from 350 nm down to 65 nm.
- CMOS, BCD, HV CMOS, mixed-signal, power
- 1.8 V – 1200 V device window
- 12–16-bit precision mixed-signal options
PDK & Design Enablement
PDKs with standard cells, I/O libraries and memory compilers — plus full design services next door.
- Cadence, Synopsys and Siemens EDA flows
- Layout, verification and DFT services
- DRC, LVS, ERC and antenna checks
Packaging & Test
Backend processing and qualification happen on-site, in the same value chain as the shuttle.
- Parametric and functional test
- Burn-in and screening on request
- Full traceability per die
Path to Volume
A proven MPW design scales to dedicated full-wafer production on the same process — no re-qualification.
- Same PDK, same fab flow
- Dedicated capacity scheduling
- AEC-Q100-oriented quality roadmap
MPW specifications
The shuttle, specified.
Reference parameters for the Multi Project Wafer service. Process-specific design rules come from the PDK for your target node, and every delivery ships with a test report and full traceability.
Shuttle Parameters
- Reticle: up to 16 tiles of 5×5 per field
- Minimum design size: 2×2 mm
- Wafer: 200 mm (8-inch)
- Cadence: target monthly, demand-aggregated
- Frontend layers: target up to 30, process-dependent
What You Receive
- 10–50 packaged units per design
- QFN or BGA packaging options
- Parametric and functional test report
- Full lot traceability
- Documentation pack for volume hand-off
Engagement Models
- MPW — shared-mask prototyping
- Dedicated — full-wafer volume production
- Co-development — custom processes and joint R&D
- A single point of contact across all three
How it works
The flow, step by step
- 01
Design Submission
Upload GDSII against the PDK for your node; the design team reviews and runs DRC screening at intake.
- 02
Shuttle Aggregation
Accepted designs are merged into the shared reticle, the mask is ordered and a fab slot is reserved.
- 03
Wafer Fabrication
The frontend fab runs lithography, etch, deposition and implant across the full process flow.
- 04
Backend Processing
Wafers are diced, die-attached and wire-bonded into QFN or BGA packages.
- 05
Test & Qualification
Parametric and functional test with 100% coverage; burn-in and screening on request.
- 06
Delivery
Packaged prototypes ship with a test report and full traceability — 8–12 weeks after tape-out.
Why it matters
One wafer, many designs, one platform.
An MPW shuttle is the cheapest honest answer to “does my design work?” — real masks, a real fab and real test, at a fraction of a dedicated run. And because the shuttle runs on the same production line as volume wafers, the step from prototype to product is a scheduling decision, not a migration.
Where it goes
Applications & industries
Fabless & Startups
Validate first silicon and demo boards before committing to dedicated masks and volume production.
Universities & Research
Academic access to industrial-grade 350–65 nm fabrication for VLSI courses, theses and research runs.
IDMs & Fabs
Overflow capacity and process diversity on mature nodes, with a quick ramp to dedicated production.
Work with MPW Services.
From engineering programs to production partnership — the MPW Services team is one message away.